This invention relates to BIMOS integrated circuits and more particularly to such an integrated circuit wherein the MOS transistors are enclosed in an N-type basket formed by an N-type buried layer and and annular N-type plug, the basket itself being in an N-type epitaxial pocket defined by isolation walls and a P-type substrate.
It is known to combine in an integrated circuit, P-channel and N-channel MOS transistors and both lateral and vertical type NPN and PNP transistors. The MOS transistors are formed in one N-type epitaxial pocket while usually each bipolar transistor is formed in its own separate pocket.
In the MOS pocket, the N-channel transistors are formed in a P-type well region which in most prior art examples extends downward from the epitaxial surface only partway through the epitaxial layer. Thus a slice of lightly N doped epitaxial material is located below the P-well. This, I believe, poses the potentially serious disadvantage that the parasitic PNPN transistor consisting of a substrate, epi-pocket, P-well and N-type source region will be formed which will more easily latch up.
The lightly doped N-type epitaxial slice represents a parasitic-transistor region of high minority carrier concentration and the PNPN will be more easily latched on by stray currents either in the epitaxial material or in the substrate. Such stray currents are more likely to exist when the bipolar transistors are carrying large currents.
This problem is solved in the BIMOS integrated structure disclosed by Miles and Emerald in U.S. Pat. No. 4,225,877, issued Sept. 30, 1980 and assigned to the same assignee as is the present invention. There, a P-type buried layer joins the P-well with the P-type substrate below and destroys the parasitic PNPN transistor. However, this structure can only be operated with the substrate and the P-well at the same voltage.
Although the first above-mentioned BIMOS integrated circuit can be operated with the MOS circuit at a different ground reference potential than that of the bipolar circuit, that difference in reference potentials would be small unless the above-mentioned slice of lightly-doped epitaxial material is made very thick to accomodate the resulting expanded depletion layer therein and also to reduce the gain of the parasitic PNPN transistor enough to prevent latch-up. Thicker epitaxial layers tend to increase the V.sub.SAT in the power NPN transistors and limit the current they may safely carry.
It is therefore an object of this invention to provide a BIMOS integrated circuit for operation of the small signal MOS transistors at one DC voltage reference level and operation of relatively high current carrying bipolar transistors at a lower DC voltage reference level.
It is a further object of this invention to provide such an integrated circuit that can be made simply by standard BIMOS processing steps.